Memory devices are typically provided as internal, semiconductor, integrated circuit devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory has developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data state (e.g., data value) of each memory cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
A NAND flash memory is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series between a pair of select gates, e.g., a source select transistor and a drain select transistor. Each source select transistor may be connected to a source, while each drain select transistor may be connected to a data line, such as column bit line. Variations using more than one select gate between a string of memory cells and the source, and/or between the string of memory cells and the data line, are known.
In programming memory, memory cells may generally be programmed as what are often termed single-level cells (SLC) or multiple-level cells (MLC). SLC may use a single memory cell to represent one digit (e.g., bit) of data. For example, in SLC, a Vt of 2.5V might indicate a programmed memory cell (e.g., representing a logical 0) while a Vt of −0.5V might indicate an erased cell (e.g., representing a logical 1). As an example, the erased state in SLC might be represented by any threshold voltage less than or equal to 0V, while the programmed data state might be represented by any threshold voltage greater than 0V.
MLC uses more than two Vt ranges, where each Vt range indicates a different data state. As is generally known, a margin (e.g., a certain number of volts), such as a dead space, may separate adjacent Vt ranges, e.g., to facilitate differentiating between data states. Multiple-level cells can take advantage of the analog nature of traditional non-volatile memory cells by assigning a bit pattern to a specific Vt range. While MLC typically uses a memory cell to represent one data state of a binary number of data states (e.g., 4, 8, 16, . . . ), a memory cell operated as MLC may be used to represent a non-binary number of data states. For example, where the MLC uses three Vt ranges, two memory cells might be used to collectively represent one of eight data states.
In programming MLC memory, data values are often programmed using more than one pass, e.g., programming one or more digits in each pass. For example, in four-level MLC (typically referred to simply as MLC), a first digit, e.g., a least significant bit (LSB), often referred to as lower page (LP) data, may be programmed to the memory cells in a first pass, thus resulting in two (e.g., first and second) threshold voltage ranges. Subsequently, a second digit, e.g., a most significant bit (MSB), often referred to as upper page (UP) data may be programmed to the memory cells in a second pass, typically moving some portion of those memory cells in the first threshold voltage range into a third threshold voltage range, and moving some portion of those memory cells in the second threshold voltage range into a fourth threshold voltage range. Similarly, eight-level MLC (typically referred to as TLC) may represent a bit pattern of three bits, including a first digit, e.g., a least significant bit (LSB) or lower page (LP) data; a second digit, e.g., upper page (UP) data; and a third digit, e.g., a most significant bit (MSB) or extra page (XP) data. In operating TLC, the LP data and the UP data may be programmed to the memory cells in a first pass, resulting in four threshold voltage ranges, followed by the XP data (and, possibly, reprogramming of the UP data) in a second pass, resulting in eight threshold voltage ranges.
In each pass, programming typically utilizes an iterative process of applying a programming pulse to a memory cell and verifying if that memory cell has reached its desired data state in response to that programming pulse, and repeating that iterative process until that memory cell passes the verification. Once a memory cell passes the verification, it may be inhibited from further programming. The iterative process can be repeated with changing (e.g., increasing) voltage levels of the programming pulse until each memory cell selected for the programming operation has reached its respective desired data state, or some failure is declared, e.g., reaching a maximum number of allowed programming pulses during the programming operation.
Due to the nature of flash memory devices, the physical location within a flash memory device for a given logical address will generally change over time. To address this changing correspondence, a Flash Translation Layer (FTL) is typically used to map the logical address to the physical address to which data has been stored. Although this high-level mapping information is often held in volatile memory for ease of use during operation of the memory device, such mapping information may also be periodically stored to non-volatile memory so that it may be retrieved during start-up of the device. Alternatively, this mapping information may be updated to non-volatile storage with each programming operation. If a memory device is powered down abruptly or otherwise loses power in an uncontrolled manner, e.g., asynchronous power loss, the most recent mapping information, as well as user data, may be invalid.
In the event of an unexpected power loss, the last written information may not be available to the host. Power loss detection algorithms may be used at a next power-up of the memory to scan its blocks of memory cells to determine where the last written information may have occurred in order to facilitate data recovery. As the number blocks of memory cells in a memory device increases, and as the number of possible data states increases, these power loss detection algorithms can become increasingly complex and time consuming, thereby slowing power-up of the memory.